1. Field of the Invention
The present invention relates to a method of inspecting whether an interconnection pattern groove formed on a surface of a substrate is successfully filled with a metal, and a manufacturing method of a semiconductor device using this inspection method and an inspection apparatus. More specifically, the present invention relates to, for example, an inspection of a degree to which a fine interconnection pattern groove with a high aspect ratio is filled with a metal in a manufacturing process of an LSI (Large Scale Integrated Circuit) or a VLSI (very large scale integrated circuit) semiconductor devices.
2. Related Background Art
Hereinafter, in a process of inspecting whether an interconnection pattern groove is successfully filled with a metal, an actual interconnection pattern cannot be directly measured because of the minuteness of the actual interconnection pattern, difficulty in a non-contact type measurement of metal film thickness and so forth. Therefore, there has been used a method in which a pattern for measurement is produced in a wafer and measuring this pattern to perform an indirect inspection. Such indirect inspection methods include a contact method of measuring a sheet resistance of a pattern for measurement by using a four-point probe method (e.g., Japanese Patent No. 2559512), a method of managing a film thickness by observing a pattern for measurement by using an optical microscope (e.g., Japanese Patent No. 2570130), a method of inspecting a filling degree of a through hole on the basis of a change in a layer resistance by using the four-point probe method or an eddy current method (e.g., Japanese Patent Laid Open (kokai) 10-154737) and others.
Since the method disclosed in Japanese Patent No. 2559512 is a contact method, it has a problem that an actual interconnection pattern cannot be directly measured. In addition, the method disclosed in Japanese Patent No. 2570130 has a problem that automation and quantification are difficult because of the measurement using an optical microscope.
Further, the method disclosed in Japanese Patent Laid Open (kokai) 10-154737 uses a principle that a void generated in a metal interconnection would contribute as a resistance to a flow of a current when a void is. It measures a filling degree of a via on the basis of a change in a layer resistance, which increases in a defective product with a void produced therein and, on the other hand, decreases the layer resistance in a non-defective product having no void.
However, with acceleration of minuteness in recent years, there have increased fine patterns such as a pattern with a high aspect ratio and a small through hole diameter, a line with a very thin width and others. When trying to measure a change in a layer resistance in such a pattern, it is hard to detect a change in the layer resistance since a current rarely flows through this fine pattern. Furthermore, in common with the methods mentioned above, there is a problem that an area in which a pattern for measurement is produced must be assigned on a wafer.
In order to solve above problems, there has been recently developed a method of directly inspecting an interconnection pattern. Examples of such direct inspection methods include a destructive inspection method in which a wafer is split off at a desired observation position and observed by using an electron microscope, a non-destructive inspection method in which a wafer having a bias voltage applied thereto is irradiated with electron beams and an inspection is carried out by obtaining a voltage contrast based on a phenomenon that the emission quantity of secondary electrons varies depending on a conductivity (change in resistance) of a material embedded as an interconnection (e.g., Japanese Patent Laid Open (kokai) 2001-313322), and others.
However, the method disclosed in Japanese Patent Laid Open (kokai) 10-154737 has a problem that considerable amounts of time and cost are consumed since a plurality of steps are required before the measurement, as well as a restriction that this method cannot be used in a product wafer because of the destructive inspection.
Moreover, although the method disclosed in Japanese Patent Laid Open (kokai) 2001-313322 is expected as a method which can inspect a filling degree of an interconnection pattern groove in a product wafer in the non-contact manner, there have been pointed out many problems that a very large and expensive apparatus is required as an inspection apparatus since a complicated structure including a vacuum system is necessary, a throughput is slow, the inspection cannot be stably performed and the like.